As the EOT (Equivalent Oxide Thickness) of gate oxides continues to approach less than 20 Angstroms as part of improved CMOS technology, it becomes mandatory to suppress boron penetration through the ultra-thin gate oxide and reduce the oxide leakage current by increasing the nitrogen concentration in the gate oxide. Decoupled-plasma nitridation (DPN) is an emerging new technology for incorporating ultra-high concentrations of nitrogen at the top surface layer of an ultra-thin gate oxide. An example of apparatus used for this is shown in FIG. 1. Through application of RF voltage to external coil 12, a nitrogen plasma is formed in chamber 11. Sample 15, whose surface is to be nitrided, sits on sample holder 14 which positions it to be just below a series of gas inlet ports 13. The key features of the process are the use of inductive coupling for plasma formation. RF power is transferred to the plasma via an RF magnetic field which in turn generates an ionizing electric field. Inductive coupling is much more efficient for plasma production than electroded systems since energy is not dissipated in driving ions into a surface. Not shown in FIG. 1 is the pumping port and throttle valve which, when used in combination with the nitrogen inlet ports 13, are used to establish the equilibrium pressure in the chamber.
Compared to earlier remote-plasma nitridation (RPN) technology, DPN improves the nitrogen uniformity and oxide leakage current considerably. However, due to its low process temperature of less than 100° C., large amount of defects are present in the gate oxide after DPN and the gate oxide integrity is significantly degraded. Hence, post-DPN annealing at high temperature is required to eliminate the oxide defects and improve the oxide integrity.
Such a need is known to the prior art. However, previous prior art practice has been to anneal in pure helium (at a temperature of 1,050° C., pressure of 50 torr, with 5 slm of He flow). These conditions have become standard procedure for the prior art because they offer several advantages, such as no additional oxide growth or nitrogen incorporation during post-DPN annealing. We have, however, determined that annealing under these conditions also has several disadvantages including a deterioration of the electrical performance of devices (such as capacitors and transistors) when they have been subjected to pure helium annealing. The present invention discloses other post-DPN annealing methods for improving the gate oxide integrity and device electrical performance.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,140,187 (DeBusk et al.) reveals a remote plasma nitridation process for a gate oxide. A He/Ar plasma is used followed by an anneal in oxygen at about 800° C. In U.S. Pat. No. 5,861,329, Yeh shows a plasma process for forming a barrier layer. Gases used included nitrogen, ammonia, nitrogen oxide, and nitrogen/oxygen mixtures. U.S. Pat. No. 6,225,169B1 (Chew) shows a RTN process in which the nitrided layer is formed on the sidewalls of the gate structure while in U.S. Pat. No. 6,162,717, Yeh et al. use a high density plasma process in which the gate dielectric becomes sandwiched between two layers of silicon nitride.